Schematic design is an important part for building any power application. With a number of Computer Aided Design (CAD) tools available in market, engineers have a choice to pick a tool of their convenience. In the process of building the application, designers use variety of components from various vendors. The vendors usually provide ready schematic modules and associated behavioral models for a typical use case of their product. These are usually design files specific to an Electronic Design Automation (EDA) tool, or design information in the datasheet. In such scenarios, engineers have to replicate the schematic and simulation setup in their design environment. This turns out to be a time consuming and error prone task. Electronic Design Interchange Format (EDIF) was developed for exchange of schematic and model data in a vendor neutral format. EDA companies started providing direct import of certain design formats, but without the export feature. Even then, with the increasing number of tool vendors and design formats, there is no single format that is supported by most of the EDA tools, and there is a need for improvement in this area. There has been some work reported on tool independent exchange of simulation models in but not on symbols and schematic. In a typical electronic design process, a designer uses a CAD tool to create a schematic, generate a netlist and run simulations. However this is a manual process and is not scalable. If a designer has to create 100 or 1000 schematics, that may have slight variations from each other, there is no automated method or tool available. One approach is to create a netlist from a schematic and then quickly create multiple netlists either manually or using some form of computer assisted manipulation. This approach will, after some extra effort, arrive at a set of netlists to allow a CAD tool to run simulations. However this approach has limitations. Though a generated netlist is fully functional (at least for simulations), it is not easy to visualize, probe, enhance and debug and therefore a schematic has to be created. In a typical application, an amplifier or a power model has to be created for 500+ devices which has typically been done using mostly manual netlist manipulation. However, a schematic is usually required for shipping a design to end customers. Further exacerbating the process, the generated netlists often encounter simulation issues such as non-convergence. Debugging such netlists (e.g., without a schematic) is a very tedious task. Another issue with prior art applications is that a schematic may be lost (e.g., not supported) due to an obsolete CAD system which is no longer supported to recreating that schematic in a different CAD system. That is, there is no common format to export from an old CAD system into a current CAD system. Thus, getting a design transferred from an obsolete (or outdated) CAD system to another may be problematic.